clock frequency
英 [klɒk ˈfriːkwənsi]
美 [klɑːk ˈfriːkwənsi]
时钟节拍频率
双语例句
- This is because process execution now needs to be coordinated across the bus, which operates at half the clock frequency of the chip.
这是因为进程执行现在需要跨总线协调，以一半的芯片时钟频率进行处理。 - Retriggerable mono MVBR NHZL times out at slightly longer than half of original clock frequency.
可重触发单MVBRNHZL时间稍长原始时钟频率的一半。 - The high clock frequency requirements will have to be weighed against the need for tighter design criteria that ensure high noise immunity.
高时钟频率的要求比高抗扰度的要求更为重要，因为高抗扰度可通过精心设计予以保证。 - The sample rate, filter corner frequency, settling time, group delay and output word rate will be reduced also, as these are proportional to the external clock frequency.
由于采样速率、滤波器转折频率、建立时间、群延迟和输出字速率与外部时钟频率呈比例变化关系，因此这些参数也会相应降低。 - The minimum clock frequency is established by leakage on the auto-zero and reference caps.
最小的时钟频率，由自动归零和基准电容的泄漏值确定。 - In digital circuits, often requires a higher clock frequency sub-band operation, a lower frequency clock signal.
在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。 - Meanwhile, the switched capacitor notch filter is designed, which can adjust center frequency freely by changing the switching clock frequency and make the center frequency highly accurate and stable.
介绍了数字化开关电容滤波技术，并设计了可以通过改变开关时钟频率来自由调整中心频率的开关电容带阻滤波器，使中心频率具有很高的精度和稳定度。 - This article mainly addresses the maintenance period of clock frequency of SPC exchanges in China's telecommunication network.
本文主要讨论我国电信网中程控交换局时钟频率维护周期的确定问题。 - The analog input is continuously sampled by an analog modulator at twice the clock frequency eliminating the need for external sample-and-hold circuitry.
模拟输入由模拟调制器以时钟频率两倍的速度连续采样，因而无需外部采样保持电路。 - The sample rate, filter corner frequencies, and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7760.
采样速率、滤波器转折频率和输出字速率由AD7760的外部时钟频率与配置寄存器共同设置。 - Studies have shown that Star clock resonant cavity temperature fluctuations in the satellite clock frequency of long-term stability of the main factors.
因此，为了得到更高的频率长期稳定度，提高星钟谐振腔的温度稳定度是非常有必要的。 - Suppose that Enable is high, the counter counts up every clock cycle, and the frequency of the PWM output is the clock frequency divided by2 count bits.
假设高信号使能，计数器每个时钟周期进行计数，PWM输出的频率为时钟频率的2次幂分频。 - Alarm clock function, can be of any MP3 song or an arbitrary FM alarm clock frequency to as tones, so that every day you wake up in the music;
闹钟功能，可以把MP3内的任意一首歌曲或任意FM频率来作为闹钟铃声，使您每天在音乐中醒来； - Besides, we can improve system performance by increasing clock frequency and selecting high efficient component, and realize high frequency signal generator and various waveform signal generator.
另外，通过提高时钟频率，并有效地选择高效率的相关器件，我们还能够对该设备进行进一步的完善和改进，从而实现高频率的信号发生器及任意波形信号发生器。 - Simulation results show the PLL clock frequency multiplier has lower phase noise and shorter capture time.
结果表明，PLL倍频器具有较低的噪声和较高的捕获速度。 - DCM can synthesize the clock frequency, phase shift and eliminate clock skew, solving many clocking issues.
DCM具有频率综合、相移功能，能够消除时钟偏移，解决很多系统中的时钟问题。 - Best frequency relation is given between IF coherent oscillating source and clock frequency of full coherent radar.
给出了全相参雷达频率源的中频相干振荡源及时钟频率之间的最佳频率关系。 - Study of carrier and sampling clock frequency synchronization performance in WiMAX system
WiMAX系统中载波与采样钟同步的研究 - In the higher clock frequency MCM, terminal-matching method can be used to control interconnection reflection.
在时钟频率较高的MCM中，可采用终端匹配技术来有效的抑制互连线上的反射噪声。 - Compared to other designs, our multiplier is pipelined to enhance the clock frequency.
与现有结构相比，由于采用了多级流水线的乘法器结构，提高了系统的时钟频率； - The increasing clock frequency and bandwidth leads to many signal integrity problems in high speed digital circuits, bringing a great challenge for hardware design of the system.
随着系统时钟频率的提高，信号带宽增加，高速数字电路中的信号完整性的诸多问题凸显，对智能视频监控系统硬件设计带来了很大挑战。 - Because of the synchronization demand of its own, parallel bus is limited in clock frequency.
传统的并行总线由于自身的同步需要，在时钟速率上受到了很大限制。 - After static timing analysis, FPGA system still have sufficient timing margin in the corresponding clock frequency when running sending and receiving parts.
进行静态时序分析后，FPGA系统中发送部分和接收部分运行在相应时钟频率下具有足够的时序余度。 - Integrating more cores on a single chip can improve the performance while keeping the clock frequency.
通过在单个芯片上集成多个高效内核，就可以在保持工作频率的条件下实现性能的提升，以获得更高的能效。 - As the clock frequency increasing, digital systems have strict requirements for clock signals 'jitter performance.
随着时钟频率的增加，数字系统对时钟信号的抖动性能提出了更严格的要求。 - Dissipation during test is mainly due to supply voltage, clock frequency and jumps in circuit.
芯片测试功耗主要取决于供电电压、时钟频率和电路中的翻转活动三方面。 - In this designed logic circuit, because the clock frequency of all the modules is different, using phase-locked loop inside the chip increases various frequency clock signals.
在所设计的逻辑电路中，因为各个模块所需时钟频率有所不同，调用了芯片内部锁相环增加了不同频率的时钟信号。 - To ensure the high speed of the system, in the base of analysis and study algorithms principle, combining the characteristics of DES/ 3DES encryption algorithm, using a fully pipelined design to improve the system clock frequency and throughput.
为了保证系统能够实现高速，本文在分析和研究算法原理的基础上，结合DES/3DES加密算法的特征，采用了全流水线结构设计，提高了系统的时钟频率和吞吐量。 - Achieve precise control of clock frequency through DDS. 3.
以DDS为核心实现对时钟频率输出的精密控制。